1. Field of the Invention
The present invention generally relates to plasma etching of semiconductor structures, and, more particularly, to an optical endpoint detection while plasma etching.
2. Description of the Related Art
Manufacturers in the electronic sectors, in particular semiconductor manufacturers, use plasma technology for a variety of surface modification and etching applications. Plasma is a mixture of electrically charged and neutral particles, including electrons, atoms, ions and free radicals, and occurs only under certain environmental circumstances. It will react with a wide variety of substances, and can be used to clean, etch or coat almost any surface without great safety efforts and liquid waste associated with other processes.
During a plasma etch process, when building up an integrated circuit chip, one has to accurately determine the etch depth. An integrated circuit chip comprises inseparably connected circuit elements fabricated onto, or within, a suitable substrate material. Most common substrates are silicon or gallium arsenide in the form of wafers. A typical integrated circuit chip may comprise twenty or more layers of semiconducting materials, one on top of the other, forming a multi-layer structure. The layers may be patterned such that the entire structure forms the various circuit elements, such as resistors, capacitors, via holes, etc. The precision of the dimensions of those circuit elements may also depend on the controllability of a plasma etch process, and in particular on the precision of an etch depth monitoring.
Etch depth monitoring, in its simplest form, may comprise calibrating a process and then simply timing the etch run. However, run-to-run etch rate variations of up to ten percent may be expected using this method. More accurate etch depth may be obtained by etching for three-quarters of the predicted etch time, measuring the etch depth, and then predicting the time required to finish the etch. This has the major drawback of being time-consuming, and therefore expensive.
Common etch depth monitoring techniques are based on the fact that there is, in most cases, a change in the spectral composition of the light emitted by the plasma when the plasma comes into contact with an underlying surface during the etch process. Basically, the optical plasma emission reacts on the change in the chemical composition and/or electrical characteristic of the discharge due to the fact of contacting an interface layer.
For an increasing number of process applications, this approach does not provide a reliable detection performance. Moreover, several etch processes may be necessary to pattern layers where the ratio of etch-exposed areas to total substrate areas is very low. Further, an endpoint signal may be disturbed by the etch of large areas with other etch characteristics. Other difficulties may arise when etching stacks of material which have no or low differences in their chemical composition, so that the event of passing this interface is very hard to detect.
A simple multi-layer structure is illustrated in FIG. 1. As can be seen, the multi-layer structure comprises several layers of dielectric material 110. Metal layers are formed at the interfaces 100 between the dielectric layers 110. The metal layers are vertically connected by via holes 120, 130, 160. The via holes may be arranged for vertically connecting an electronic device 140 that is embedded in the multi-layer structure, for instance to connect the electronic device 140 with the top metal layer.
As can further be seen, the via hole 160 is enlarged to provide a more detailed view. The enlarged depiction 170 illustrates that the via hole 160 does not exactly end at the metal layer 190 so that the via hole 160 is shifted or offset into its lower dielectric layer. This shifting 180 of the via hole 160 may be caused by a conventional, inaccurate etch endpoint process, due to the above-described problems occurring with known etch depth monitoring techniques.
It is to be noted that an inaccurate etch endpoint process does not only affect dimensions of the illustrated via hole 160. Furthermore, all electronic devices embedded in any structure can be affected.
An inaccurate etch endpoint process is disadvantageous because for inaccurately etched structures it is difficult to predict parameters of the electronic devices and therefore it is difficult to predict the circuitry behavior. Further, for instance, inaccurately etched devices may require a re-manufacture or a redesign of the integrated circuit chip or may even require additional circuits to be provided to calibrate critical parameters.
The present invention is directed to various methods and systems that may solve, or at least reduce, some or all of the aforementioned problems.